CHAPTER 20

Resource estimation: from circuits to machines

Learning goals. Allocate a failure budget, choose a code distance under assumptions, include non-Clifford throughput, and interpret dated architecture estimates.

20.1 Begin with a workload, not a qubit count

A useful resource estimate specifies the algorithm, input size, target observable or answer, numerical precision, allowed failure probability, logical circuit, compilation strategy, hardware model, error-correction protocol, and elapsed-time target. Omitting one can change the result by orders of magnitude.

Distinguish data logical qubits from temporary workspace, routing regions, and magic-state factories. Distinguish logical gate count, depth, and runtime. A “logical qubit” is not a universal conversion unit with a fixed physical cost.

20.2 A failure budget

Suppose an algorithm has L relevant fault locations, each with failure probability at most pL. The union bound gives

$$\Pr(\text{at least one failure})\le Lp_L.$$

It does not require independence. It can be loose and assumes the locations and per-location risks are correctly defined. If independent identical events are assumed, the exact probability is $1-(1-p_L)^L$.

For total failure target ε, a conservative allocation is $p_L\le\epsilon/L$. With $L=10^8$ and ε=0.01, the required per-location error is at most $10^{-10}$. A physical gate fidelity that looks excellent in isolation can therefore still be far from sufficient for a long algorithm.

Multiple error sources need a shared budget. For example, allocate ε among memory, logical Clifford operations, magic states, algorithmic approximation, and measurement inference. The allocation can be optimized; simply ignoring several components understates the risk.

20.3 Solve an illustrative distance requirement

Use the explicitly assumed model

$$p_L=A(p/p_\mathrm{th})^{(d+1)/2}.$$

For p<pth, requiring $Lp_L\le\epsilon$ gives

$$\frac{d+1}{2}\ge \frac{\ln(\epsilon/(LA))}{\ln(p/p_\mathrm{th})},$$

where dividing by the negative denominator reverses the intermediate inequality. Thus choose the smallest supported odd d satisfying

$$d\ge 2\frac{\ln(\epsilon/(LA))}{\ln(p/p_\mathrm{th})}-1.$$

Worked estimate. Let A=0.1,p=0.001,pth=0.01,L=$10^8$, and ε=0.01. Then ε/(LA)=$10^{-9}$ and p/pth=$10^{-1}$, giving $(d+1)/2\ge9$, so d=17. A bare rotated patch uses $2(17)^2-1=577$ physical qubits.

For 100 data logical patches alone, that is 57,700 physical qubits. It omits factories, routing, spare capacity, leakage-removal hardware, and architecture-specific overhead. The numerical result is an educational model, not a prediction for a named processor.

20.4 Time and throughput

If a logical operation uses approximately d code cycles and the cycle time is τ, a depth-D sequential schedule takes roughly Ddτ. This is only a stated schedule model. Some operations have different costs, some run in parallel, and decoding or communication can add delays.

Suppose D=$10^6$,d=17,τ=1 microsecond. The model gives 17 seconds. If an algorithm consumes $10^8$ magic states and factories jointly produce $10^5$ per second, factory supply alone requires at least 1,000 seconds unless buffered or overlapped with other work. The longer bottleneck dominates an optimistic total schedule.

Classical control also matters. Syndrome streams must be decoded at sufficient throughput. A non-Clifford feed-forward decision may impose a latency constraint even when average throughput is adequate. Cooling, calibration, retries, loading, and interconnect heralding can reduce available duty cycle.

20.5 Comparing contemporary estimates

Gidney and Ekerå’s 2021 study estimated RSA-2048 factoring in eight hours using about twenty million noisy qubits under a specified superconducting-style architecture [51]. Gidney’s 2025 analysis estimated fewer than a million noisy qubits and less than a week with different arithmetic and error-correction arrangements, while retaining stated assumptions including a 0.1% gate error and one-microsecond code cycle [52].

The March 2026 Cain et al. preprint analyzes reconfigurable atomic architectures with high-rate codes and argues that cryptographically relevant Shor instances may be possible at much smaller physical counts [53]. Its headline count must be read alongside the targeted instance, gate times, connectivity, memory, decoding, and runtime assumptions. A small qubit estimate and a fast estimate are not necessarily the same estimate.

These studies are estimates, not demonstrated attacks. Improvements can arise from algorithms, coding, architecture, and scheduling, so extrapolating a single old qubit number as an immutable requirement is scientifically inappropriate. Equally, quoting only the smallest new headline count hides essential conditions.

20.6 Sensitivity and uncertainty

Resource inputs have uncertainty and may not remain stable as a machine scales. A pL model calibrated on small patches may encounter correlated-error floors, fabrication defects, or decoder limitations. Hardware errors differ by gate, qubit, context, and time. A scalar p is a simplification whose adequacy must be assessed.

A good estimate varies uncertain parameters and identifies what drives the result. If halving physical error reduces distance and factory overhead dramatically, improving fidelity may matter more than adding raw qubits. If the workload is communication-limited, faster local gates alone may have little effect.

Avoid false precision. A model producing 57,700 qubits does not imply engineering certainty to the last hundred. Report the model, rounded conclusions, and sensitivity range. Detailed spreadsheets or scripts are useful because they make assumptions inspectable and replaceable.

20.7 Exercises